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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 58: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
-3
-2
-1
(XC)
-1
(XQ)
-1L
Units
Maximum Frequency
F MAX
F MAX_PATDET
F MAX_MULT_NOMREG
F MAX_MULT_NOMREG_PATDET
F MAX_PREADD_MULT_NOADREG
F MAX_PREADD_MULT_NOADREG_PATDET
F MAX_NOPIPELINEREG
F MAX_NOPIPELINEREG_PATDET
With all registers used
With pattern detector
Two register multiply without
MREG
Two register multiply without
MREG with pattern detect
Without ADREG
Without ADREG with pattern
detect
Without pipeline registers
(MREG, ADREG)
Without pipeline registers
(MREG, ADREG) with pattern
600
551
356
327
398
398
266
250
540
483
311
286
347
347
233
219
450
408
262
241
292
292
196
184
450
408
262
241
292
292
196
184
410
356
224
211
254
254
171
160
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
detect
Configuration Switching Characteristics
Table 59: Configuration Switching Characteristics
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
Power-up Timing Characteristics
T PL (1)
T POR (1)
T ICCK
T PROGRAM
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
5
15/55
400
250
5
15/55
400
250
5
15/55
400
250
5
15/60
400
250
ms, Max
ms, Min/Max
ns, Min
ns, Min
Master/Slave Serial Mode Programming Switching
T DCCK /T CCKD
T DSCCK /T SCCKD
T CCO
F MCCK
F MCCKTOL
F MSCCK
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT at 2.5V
DOUT at 1.8V
Maximum CCLK frequency, serial modes
Frequency Tolerance, master mode with respect to
nominal CCLK.
Slave mode external CCLK
4.0/0.0
4.0/0.0
6
6
105
55
100
4.0/0.0
4.0/0.0
6
6
105
55
100
4.0/0.0
4.0/0.0
6
6
105
55
100
4.5/0.0
5.0/0.0
7
7
70
60
100
ns, Min
ns, Min
ns, Max
ns, Max
MHz, Max
%
MHz
SelectMAP Mode Programming Switching
T SMDCCK /T SMCCKD
T SMCSCCK /T SMCCKCS
SelectMAP Data Setup/Hold
CSI_B Setup/Hold
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
5.5/0.0
5.5/0.0
ns, Min
ns, Min
T SMCCKW /T SMWCCK
RDWR_B Setup/Hold
10.0/0.0 10.0/0.0 10.0/0.0 16.0/0.0
ns, Min
T SMCKCSO
T SMCO
CSO_B clock to out
(330 Ω pull-up resistor required)
CCLK to DATA out in readback at 2.5V
CCLK to DATA out in readback at 1.8V
6
6
6
6
6
6
6
6
6
7
7
7
ns, Max
ns, Max
ns, Max
DS152 (v3.6) March 18, 2014
Product Specification
49
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